1. Field of the Invention
The present invention relates to a SRAM cell, particularly to a Schmitt trigger-based FinFET SRAM cell.
2. Description of the Related Art
Embedded memories are used in various hardwares to store data, such as communication products, consumer electronic products, microprocessors. Electronic products are getting smaller and smaller, and the semiconductor industry is persistently devoted to reducing the size of semiconductor elements (such as MOSFET) so as to increase the speed, performance and density of IC and decrease the unit cost of IC. However, variance and uncertainty of MOSFET properties rises with reduction of MOSFET size. The current SRAM design has been evolved to pursue low voltage and high speed. In the design of a low-voltage memory, the achievable minimum operating voltage of 6T SRAM is limited by write failure and read interference. Facing the development of nanometric components, some researchers begin to design new structures for components. For example, the traditional planar gate is transformed to three-dimensionalized to have a fin-like structure, i.e. the so-called FinFET. The three-dimensional gate structure of FinFET can more effectively control the channel and inhibit leakage current caused by the punch-through effect. Therefore, FinFET has higher controllability over the gate than the traditional FET. Further, FinFET can greatly reduce the size of semiconductor chips and the power consumed by each logical gate.
Refer to FIG. 1 a diagram schematically showing a 6T SRAM cell. A 6T SRAM comprises a memory cell 10 containing a pair of cross coupled inverters 12 and 14, a first pass transistor 28, and a second pass transistor 30. The storage node 16 of the first inverter 12 is connected with the gates of a p-type transistor 18 and an n-type transistor 20 of the inverter 14. The storage node 22 of the inverter 14 is connected with the gates of a p-type transistor 24 and an n-type transistor 26 of the inverter 12. The n-type transistor 26 of the inverter 12 is grounded. The p-type transistor 24 of the inverter 12 is connected with a supply voltage Vcs. The n-type transistor 20 of the inverter 14 is grounded. The p-type transistor 18 of the inverter 14 is connected with the supply voltage Vcs. The first pass transistor 28 is connected with a bit line BL and controls the output of the storage node 16 of the inverter 12. The second pass transistor 30 is connected with a complementary bit line BR and controls the output of the storage node 22 of the inverter 14. The first pass transistor 28 and the second pass transistor 30 are controlled by a common write line WL. In a read activity, the bit lines BL and BR are charged to “1”—a high potential. Suppose that the storage node 16 of the inverter 12 stores data “0” and that the storage node 22 of the inverter 14 stores data “1”. In the start of a read activity, the write line turns on the first pass transistor 28 and the second pass transistor 30. The storage node 16 storing data “0” is successfully discharged by the bit line BL via the path of the n-type transistor 26 of the inverter 12. When the first pass transistor 28 and the second pass transistor 30 are both turned on, the first pass transistor 28 and the n-type transistor 26 of the inverter 12 forms a bleeder circuit. The storage node 16 originally storing data “0” has a read disturb. In a low operating voltage environment, the voltage of the storage node 16 plus the noise of the inverter 12 and first pass transistor 28 is likely to exceed the trip voltage of the inverter 14 and reword the data stored in the inverter 14. Thus is caused a read error.
Refer to FIG. 2 for a design to overcome the noise-and-low operating voltage-induced read error of a 6T SRAM cell. In FIG. 2, four transistors are added to the original 6T SRAM cell to form a 10T SRAM cell. The transistors in FIG. 1 and FIG. 2 are all FinFETs. In FIG. 2, the first pass transistor 28 is connected with the gate of a third pass transistor 32, and the drain of the third pass transistor 32 is connected with the supply voltage Vcs. The n-type transistor of the inverter 12 is further connected with an n-type transistor 34. The n-type transistor 34 is grounded, and the source of the third pass transistor 32 is connected with the drains of the n-type transistors 26 and 34. The second pass transistor 30 is connected with a fourth pass transistor 36, and the drain of the fourth pass transistor 36 is connected with the supply voltage Vcs. The n-type transistor 20 of the inverter 14 is further connected with an n-type transistor 38. The n-type transistor 38 is grounded, and the source of the fourth pass transistor 36 is connected with the drains of the n-type transistors 20 and 38. In the start of a read activity, the write line WL turns on the first and second pass transistors 28 and 30. The conduction state of the third pass transistor 32/fourth pass transistor 36 is determined according to whether “0” or “1” is stored in the storage node. The storage node 16 storing “0” is successfully discharged by the bit line BL via the path of the n-type transistors 26 and 34 of the inverter 12. The storage node 22 of the inverter 14 is at the supply voltage. The node between the drains of the n-type transistors 20 and 38 has a voltage of the supply voltage Vcs minus the threshold voltage Vt of the fourth pass transistor 36. Thus is effectively increased the drain voltage of the n-type transistor 38 and the trip voltage of the inverter 14. In a low operating voltage environment, the read disturb of the storage node 16 plus the noise is still far below the trip voltage of the inverter 14. Thus is increased RSNM (Read Static Noise Margin) and avoided read errors. Refer to FIG. 3. The gates of the third pass transistor 32 and the fourth pass transistor 36 are connected with the word line WL and turned on in a read and write activity. The drains of the third pass transistor 32 and fourth pass transistor 36 are respectively connected with the bit line BL and the complementary bit line BR. Thereby, a write word line WWL turns on the first pass transistor 28 and the second pass transistor 30 in a write activity; the word line WL regulates the turn-on timing of the third pass transistor 32 and fourth pass transistor 36. The SRAM cell in FIG. 3 outperforms the SRAM cell in FIG. 2 in that the smaller voltage-division effect would not cause errors in a read activity. However, a SRAM cell containing ten transistors occupies too great an area and is hard to promote the chip density. Further, a SRAM cell having a greater area would have higher power consumption and lower performance.
Accordingly, the present invention proposes a Schmitt trigger-based FinFET SRAM cell to overcome the abovementioned problems.